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EVALUATION KIT AVAILABLE
TC500 TC500A TC510 TC514
1
PRECISION ANALOG FRONT ENDS
FEATURES
s s s s s s s s s Precision (up to 17 Bits) A/D Converter "Front End" 3-Pin Control Interface to Microprocessor Flexible: User Can Trade-Off Conversion Speed for Resolution Single Supply Operation (TC510/514) 4 Input, Differential Analog MUX (TC514) Automatic Input Voltage Polarity Detection Low Power Dissipation ........... TC500/500A: 10mW TC510/514: 18mW Wide Analog Input Range ....... 4.2V (TC500A/510) Directly Accepts Bipolar and Differential Input Signals
GENERAL DESCRIPTION
The TC500/500A/510/514 family are precision analog front ends that implement dual slope A/D converters having a maximum resolution of 17 bits plus sign. As a minimum, each device contains the integrator, zero crossing comparator and processor interface logic. The TC500 is the base (16 bit max) device and requires both positive and negative power supplies. The TC500A is identical to the TC500, except it has improved linearity allowing it to operate to a maximum resolution of 17 bits. The TC510 adds an onboard negative power supply converter for single supply operation. The TC514 adds both a negative power supply converter and a 4 input differential analog multiplexer. Each device has the same processor control interface consisting of 3 wires: control inputs A and B and zerocrossing comparator output (CMPTR). The processor manipulates A, B to sequence the TC5xx through four phases of conversion: Auto Zero, Integrate, Deintegrate and Integrator Zero. During the Auto Zero phase, offset voltages in the TC5xx are corrected by a closed-loop feedback mechanism. The input voltage is applied to the integrator during the Integrate phase. This causes an integrator output dv/dt directly proportional to the magnitude of the input voltage. The higher the input voltage, the greater the magnitude of the voltage stored on the integrator during this phase. At the start of the Deintegrate phase, an external voltage reference is applied to the integrator, and at the same time, the external host processor starts its on-board timer. The processor mainRINT - VREF CAZ BUF
CAZ INTEGRATOR - CMPTR 1 + + - + CINT CINT CONTROL LOGIC CONVERTER STATE B 0 ZERO INTEGRATOR OUTPUT 1 AUTO-ZERO 0 SIGNAL INTEGRATE 1 DEINTEGRATE
2 3 4 5 6 7
DGND
ORDERING INFORMATION
Part No.
TC500ACOE TC500ACPE TC500COE TC500CPE TC510COG TC510CPF TC514COI TC514CPJ TC500EV
Package
16-Pin SOIC 16-Pin Plastic DIP (Narrow) 16-Pin SOIC 16-Pin Plastic DIP (Narrow) 24-Pin SOIC 24-Pin Plastic DIP (300 Mil.)
Temp. Range
0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C
28-Pin SOIC 0C to +70C 28-Pin Plastic DIP (300 Mil.) 0C to +70C Evaluation Kit for TC500/500A/510/514
FUNCTIONAL BLOCK DIAGRAM
CREF
A0 A1 A 0 0 1 1
+ CREF
+ VREF
- CREF BUFFER -
CH1 + + CH2 CH3 + CH4 + CH1 - CH2 - CH3 - CH4 -
ACOM
SWR SWR
DIF. MUX (TC514)
SWI - SWRI + SWRI
+
TC500 TC500A TC510 CMPTR 2 TC514
- LEVEL SHIFT CMPTR OUTPUT
SWZ
+ SWRI
- SWRI SW1
SWIZ SWZ POLARITY DETECTION
ANALOG SWITCH CONTROL SIGNALS
SWI VS OSC
DC-TO-DC CONVERTER (TC510 & TC514)
PHASE DECODING LOGIC
- VOUT
CAP- CAP+ VSS (TC500 TC500A)
1.0F
A
B
- COUT
1.0F
CONTROL LOGIC
TC500/A/510/514-3 10/3/96
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TELCOM SEMICONDUCTOR, INC.
PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514
GENERAL DESCRIPTION (Cont.)
tains this state until a transition occurs on the CMPTR output, at which time the processor halts its timer. The resulting timer count is the converted analog data. Integrator Zero (the final phase of conversion) removes any residue remaining in the integrator in preparation for the next conversion. The TC500/500A/510/514 offer high resolution (up to 17 bits) superior 50Hz/60Hz noise rejection, low power operation, minimum I/O connections, low input bias currents and lower cost compared to other converter technologies having similar conversion speeds. TC500/500A Negative Supply Voltage (VSS to GND) ...................................................... - 8V _ Analog Input Voltage (V+ or V IN) .................... VDD to VSS IN Logic Input Voltage .................. VDD +0.3V to GND - 0.3V Voltage on OSC ..... - 0.3V to (VDD +0.3V) for VDD < 5.5V Ambient Operating Temperature Range ...... 0C to +70C Storage Temperature Range ................ - 65C to +150C Lead Temperature (Soldering, 10 sec) ................. +300C
* Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
TC510/514 Positive Supply Voltage (VDD to GND) .................................................. +10.5V TC500/500A Supply Voltage (VDD to VSS) ....................................................... +18V TC500/500A Positive Supply Voltage (VDD to GND) ..................................................... +12V
ELECTRICAL CHARACTERISTICS: TC510/514: VDD = +5V, TC500/500A: VS = 5V unless otherwise
specified. CAZ = CREF = 0.47 F TA = +25C Symbol Parameter Analog
ZSE ENL NL ZSTC Resolution Zero-Scale Error with Auto Zero Phase End Point Linearity Best Case Straight Line Linearity Zero-Scale Temperature Coefficient Full-Scale Symmetry Error (Roll-Over Error) Full-Scale Temperature Coefficient Note 1 TC500/510/514 TC500A TC500/510/514, Notes 1, 2, TC500A TC500/510/514, Notes 1, 2, TC500A Over Operating Temperature Range Note 3 Over Operating Temperature Range External Reference TC = 0ppm/C VIN = 0V 60 -- -- -- -- -- -- -- -- -- -- 0.005 -- 0.003 -- -- -- 0.005 0.003 0.015 0.010 0.008 0.005 -- -- -- -- -- -- -- -- -- 0.005 0.003 0.015 0.010 -- -- 1 -- 0.012 0.009 0.060 0.045 -- -- 2 V % F.S. % F.S. % F.S. % F.S. % F.S. V/C
TA = 0C to +70C Max Min Typ Max Unit
Test Conditions
Min
Typ
SYE FSTC
-- --
0.01 --
-- --
-- --
0.03 10
-- --
% F.S. ppm/C
IIN VCMR
Input Current Common-Mode Voltage Range Integrator Output Swing Analog Input Signal Range ACOM = GND = 0V Voltage Reference Range V REF V+ REF
_
-- VSS +1.5 VSS +0.9 VSS +1.5 VSS +1
6 -- -- -- --
-- -- VDD - 1.5 VSS +1.5 VDD - 0.9 VSS +0.9 VDD - 1.5 VSS +1.5 VDD - 1 VSS +1
-- -- -- -- --
-- VDD - 1.5 VSS +0.9 VSS +1.5 VDD - 1
pA V V V V
VREF
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PRECISION ANALOG FRONT ENDS
TC500 TC500A TC510 TC514
1
ELECTRICAL CHARACTERISTICS: (Cont.)
TA = +25C Symbol Digital
VOH VOL VIH VIL IL tD Comparator Logic 1, Output High Comparator Logic 0, Output Low Logic 1, Input High Voltage Logic 0, Input Low Voltage Logic Input Current Comparator Delay ISOURCE = 400A ISINK = 2.1mA 4 -- 3.5 -- -- -- -- -- -- -- -- 2 -- 0.4 -- 1 -- -- 4 -- 3.5 -- -- -- -- -- -- -- 0.3 3 -- 0.4 -- 1 -- -- V V V V A sec V k
TA = 0C to +70C Max Min Typ Max Unit
2 3 4 5 6 7
Parameter
Test Conditions
Min
Typ
Logic 1 or 0
Multiplexer (TC514 Only)
RDSON IS PD VDD ROUT IOUT IS PD VDD VSS Maximum Input Voltage Drain/Source ON Resistance VDD = 5V VDD = 5V VDD = 5V, A = 1, B = 1 VDD = 5V - 2.5 -- -- 6 2.5 10 - 2.5 -- -- -- 2.5 --
Power (TC510/514 Only)
Supply Current Power Dissipation Positive Supply Operating Voltage Range Operating Source Resistance Oscillator Frequency (Note 3) Maximum Current Out -- -- 4.5 -- -- -- 1.8 18 -- 60 100 -- 2.4 -- 5.5 85 -- - 10 -- -- 4.5 -- -- -- -- -- -- -- -- -- 3.5 -- 5.5 100 -- - 10 mA mW V kHz mA
IOUT = 10mA VDD = 5V VS = 5V, A = B = 1 VDD = 5V, VSS = - 5V
Power (TC500/500A Only)
Supply Current Power Dissipation Positive Supply Operating Voltage Range Negative Supply Operating Voltage Range -- -- 4.5 - 4.5 1 10 -- -- 1.5 -- 7.5 - 7.5 -- -- 4.5 - 4.5 -- -- -- -- 2.5 -- 7.5 - 7.5 mA mW V V
NOTES: 1. Integrate time 66msec, auto-zero time 66msec, VINT (peak) 4V. 2. End point linearity at 1/4, 1 /2, 3/4 F.S. after full-scale adjustment. 3. Roll-over error is related to CINT, CREF, CAZ characteristics.
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PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514
PIN CONFIGURATIONS
CINT 1 VSS 2 CAZ 3 BUF 4 ACOM
- +
16 VDD 15 DIGITAL GND 14 CMPTR OUT 13 B
CINT VSS CAZ BUF ACOM CREF CREF VREF
- + -
1 2 3 4 5 6 7 8
16 15 14
VDD DIGITAL GND CMPTR OUT B A
+ VIN - VIN +
5
CREF 6 CREF 7 VREF 8
-
TC500/ TC500A 12 A + CPE 11 VIN
10 VIN 9 VREF
+ -
TC500/ TC500A COE
13 12 11 10 9
VREF
- VOUT 1 CINT 2 CAZ 3
24 CAP - 23 DGND 22 CAP +
- VOUT
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19
CAP - DGND CAP + VDD OSC CMPTR OUT A B VIN VIN N/C N/C
- +
CINT CAZ BUF ACOM - CREF CREF
- V REF + V REF +
BUF ACOM C- CREF
- V REF + V REF REF +
4 5 6 7 8 9
21 VDD 20 OSC
TC510CPF
19 CMPTR OUT 18 17 A B
+
TC510COG
18 17 16 15 14 13
16 VIN
- 15 VIN
N/C 10 N/C 11 N/C 12
N/C N/C N/C
14 N/C 13 N/C
- VOUT
1 2 3 4 5 6 7 8 9
28 CAP - 27 DGND 26 CAP + 25 VDD 24 OSC
- VOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
CAP - DGND CAP + VDD OSC CMPTR OUT A B A0 A1 CH1+ CH2+ CH3+ CH4+
CINT CAZ BUF ACOM - CREF
+ CREF - V REF + V REF
CINT CAZ BUF ACOM - CREF
+ CREF - V REF + V REF
TC514CPJ
23 CMPTR OUT 22 21 A B
TC514COI
22 21 20 19 18 17 16 15
20 A0 19 A1 18 CH1+ 17 CH2+ 16 CH3+ 15 CH4+
CH4- 10 CH3- 11 CH2- 12 CH1- 13 N/C 14
CH4- CH3- CH2- CH1- N/C
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PRECISION ANALOG FRONT ENDS
TC500 TC500A TC510 TC514
1
PIN DESCRIPTION
Pin No Pin No (TC500, 500A) (TC510)
1 2 3 4 5 2 Not Used 3 4 5
Pin No (TC514)
2 Not Used 3 4 5
Symbol
CINT VSS CAZ BUF ACOM
Description
Integrator output. Integrator capacitor connection. Negative power supply input (TC500/500A only). Auto-zero input. The Auto-zero capacitor connection. Buffer output. The Integrator capacitor connection. This pin is grounded in most applications. It is recommended that - ACOM and the input common pin (VIN or C- ) be within the HN analog common mode range (CMR). Input. Negative reference capacitor connection. Input. Positive reference capacitor connection. Input. External voltage reference (-) connection. Input. External voltage reference (+) connection. Negative analog input. Positive analog input. Input. Converter phase control MSB. (See input B.) Input. Converter phase control LSB. The states of A, B place the TC5xx in one of four required phases. A conversion is complete when all four phases have been executed: 00: Integrator Zero 01: Auto Zero Phase control input pins: AB = 10: Integrate 11: Deintegrate Zero crossing comparator output. CMPTR is HIGH during the Integration phase when a positive input voltage is being integrated and is LOW when a negative input voltage is being integrated. A HIGH-to-LOW transition on CMPTR signals the processor that the Deintegrate phase is completed. CMPTR is undefined during the Auto-Zero phase. It should be monitored to time the Integrator Zero phase (see text). Input. Digital ground. Input. Power supply positive connection. Input. Negative power supply converter capacitor (+) connection. Input. Negative power supply converter capacitor (-) connection. Output. Negative power supply converter output and reservoir capacitor connection. This output can be used to power other devices in the circuit requiring a negative bias voltage. Oscillator control input. The negative power supply converter normally runs at a frequency of 100kHz. The converter oscillator frequency can be slowed down (to reduce quiescent current) by connecting an external capacitor between this pin and VDD. (See Typical Characteristics Curves). Positive analog input pin. MUX channel 1. Negative analog input pin. MUX channel 1. Positive analog input pin. MUX channel 2. Negative analog input pin. MUX channel 2. Positive analog input pin. MUX channel 3. Negative analog input pin. MUX channel 3. Positive analog input pin. MUX channel 4.
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2 3 4 5 6 7
6 7 8 9 10 11 12 13
6 7 8 9 15 16 18 17
6 7 8 9 Not Used Not Used 22 21
- CREF + CREF - VREF + VREF - VIN + VIN A B
14
19
23
CMPTR OUT
15 16
23 21 22 24 1
27 25 26 28 1
DGND VDD + CAP CAP- - VOUT
20
24
OSC
18 13 17 12 16 11 15
CH1+ - CH1 CH2+ CH2- CH3+ - CH3 CH4+
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PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514
PIN DESCRIPTION (Cont.)
Pin No (TC500/A) Pin No (TC510) Pin No (TC514)
10 20 19
Symbol
CH4- A0 A1
Description
Negative analog input pin. MUX channel 4 Multiplexer input channel select input LSB. (See A1). Multiplexer input channel select input MSB. 00 = Channel 1 01 = Channel 2 Phase control input pins: A1, A0 = 10 = Channel 3 11 = Channel 4
GENERAL THEORY OF OPERATION Dual-Slope Conversion Principles (Figure 2)
Actual data conversion is accomplished in two phases: input signal Integration and reference voltage Deintegration. The integrator output is initialized to 0V prior to the start of Integration. During Integration, analog switch S1 connects VIN to the integrator input where it is maintained for a fixed time period (tINT). The application of VIN causes the integrator output to depart 0V at a rate determined by the magnitude of VIN, and a direction determined by the polarity of VIN. The Deintegration phase is initiated immediately at the expiration of tINT.
During Deintegration, S1 connects a reference voltage (having a polarity opposite that of VIN) to the integrator input. At the same time, an external precision timer is started. The Deintegration phase is maintained until the comparator output changes state, indicating the integrator has returned to its starting point of 0V. When this occurs, the precision timer is stopped. The Deintegration time period (tDEINT), as measured by the precision timer, is directly proportional to the magnitude of the applied input voltage. A simple mathematical equation relates the Input Signal, Reference Voltage and Integration time:
CINT RINT INTEGRATOR - + VINT - + PHASE CONTROL
TC510
COMPARATOR CMPTR OUT
ANALOG INPUT (VIN)
REF VOLTAGE
S1 SWITCH DRIVER POLARITY CONTROL
CONTROL LOGIC
A
INTEGRATOR OUTPUT
B I/O
VIN VIN TINT TDEINT
VFULL SCALE 1/2 VFULL SCALE
VSUPPLY VINT
MICROCOMPUTER ROM RAM TIMER COUNTER
Figure 2. Basic Dual-Slope Converter 3-24
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PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514
NORMAL MODE REJECTION (dB)
1
1 RINT CINT
0
tINT
VIN (t) dt =
VREF tDEINT RINT CINT
30 T = MEASUREMENT PERIOD 20
2 3
where: VREF = Reference Voltage tINT = Signal Integration time (fixed) tDEINT = Reference Voltage Integration time (variable) For a constant VIN: t VIN = VREF DEINT tINT The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Input noise spikes are integrated (averaged to zero) during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments. Integrating converters provide inherent noise rejection with at least a 20dB/decade attenuation rate. Interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed since the average value of a sine wave of frequency (1/t) averaged over a period (t) is zero. Integrating converters often establish the integration period to reject 50/60Hz line frequency interference signals. The ability to reject such signals is shown by a normal mode rejection plot (Figure 4). Normal mode rejection is limited in practice to 50 to 65dB, since the line frequency can deviate by a few tenths of a percent (Figure 3).
10
0 0.1/T
1/T INPUT FREQUENCY
10/T
Figure 4.. Integrating Converter Normal Mode Rejection
TC500/500A/510/514 CONVERTER OPERATION
The TC500/500A/510/514 incorporates an Auto zero and Integrator phase in addition to the input signal Integrate and reference Deintegrate phases. The addition of these phases reduce system errors and calibration steps, and shorten overrange recovery time. A typical measurement cycle uses all four phases in the following order: (1) Auto zero (2) Input signal integration (3) Reference deintegration (4) Integrator output zero The internal analog switch status for each of these phases is summarized in Table 1. This table is referenced to the Functional Block Diagram on the first page of this data sheet.
4 5 6 7
80
NORMAL MODE REJECTION (dB)
70 t = 0.1 sec 60 50 40 30
Auto-Zero Phase (AZ)
During this phase, errors due to buffer, integrator and comparator offset voltages are nulled out by charging CAZ (auto-zero capacitor) with a compensating error voltage. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to analog common. The reference capacitor is charged to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capacitor with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages.
DEV NORMAL SIN 60 t (1 100 ) MODE = 20 LOG 60 t (1 DEV) REJECTION 100 DEV = DEVIATION FROM 60 Hz t = INTEGRATION PERIOD
20 0.01 0.1 1.0 LINE FREQUENCY DEVIATION FROM 60 Hz (%)
Figure 3. Line Frequency Deviation
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TC500 TC500A TC510 TC514
Table 1. Internal Analog Gate Status
PRECISION ANALOG FRONT ENDS
Internal Analog Gate Status Conversion Phase
Auto-Zero (A = 0, B = 1) Input Signal Integration (A = 1, B = 0) Reference Voltage Deintegration (A =1, B= 1) Integrator Output Zero (A = 0, B = 0)
SWI
Closed
+ SWRI
- SWRI
SWZ
Closed
SWR
Closed
SW1
Closed
SWIZ
Closed* Closed
Closed Closed Closed
- *Assumes a positive polarity input signal. SWRI would be closed for a negative input signal.
Analog Input Signal Integration Phase (INT)
The TC5xx integrates the differential voltage between + - the (VIN) and (VIN) inputs. The differential voltage must be within the device's common-mode range VCMR. The input signal polarity is normally checked via software at the end of this phase: CMPTR = 1 for positive polarity; CMPTR = 0 for negative polarity. voltage range, common-mode rejection is typically 80dB. Full accuracy is maintained, however, when the inputs are no less than 1.5V from either supply. The integrator output also follows the common-mode voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a large, positive common-mode voltage with a near full-scale negative differential input voltage is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common-mode voltage. For these critical applications, the integrator swing can be reduced. The integrator output can swing within 0.9V of either supply without loss of linearity.
Reference Voltage Deintegration Phase (DINT)
The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. An externally-provided, precision timer is used to measure the duration of this phase. The resulting time measurement is proportional to the magnitude of the applied input voltage.
Analog Common
Analog common is used as VIN return during system- zero and reference deintegrate. If VIN is different from analog common, a common-mode voltage exists in the system. This signal is rejected by the excellent CMR of the converter. - In most applications, VIN will be set at a fixed known voltage (i.e., power supply common). A common-mode voltage will - exist when VIN is not connected to analog common.
- Differential Reference (V+ , VREF) REF
Integrator Output Zero Phase (IZ)
This phase guarantees the integrator output is at 0V when the Auto Zero phase is entered and that only system offset voltages are compensated. This phase is used at the end of the reference voltage deintegration phase and MUST be used for ALL TC5xx applications having resolutions of 12 bits or more. If this phase is not used, the value of the AutoZero capacitor (CAZ) must be about 2 to 3 times the value of the integration capacitor (CINT) to reduce the effects of charge-sharing. The Integrator Output Zero phase should be programmed to operate until the Output of the Comparator returns "HIGH". The overall Timing System is shown in Figure 8.
ANALOG SECTION + - Differential Inputs (VIN, VIN)
The TC5xx operates with differential voltages within the input amplifier common-mode range. The amplifier common-mode range extends from 1.5V below positive supply to 1.5V above negative supply. Within this common-mode
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The reference voltage can be anywhere within 1V of the power supply voltage of the converter. Roll-over error is caused by the reference capacitor losing or gaining charge due to stray capacitance on its nodes. The difference in reference for (+) or (-) input voltages will cause a roll-over error. This error can be minimized by using a large reference capacitor in comparison to the stray capacitance.
Phase Control Inputs (A, B)
The A, B unlatched logic inputs select the TC5xx operating phase. The A, B inputs are normally driven by a microprocessor I/O port or external logic. TELCOM SEMICONDUCTOR, INC.
PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514
Comparator Output
By monitoring the comparator output during the fixed signal integrate time, the input signal polarity can be determined by the microprocessor controlling the conversion. The comparator output is HIGH for positive signals and LOW for negative signals during the signal-integrate phase (see timing diagram). During the reference deintegrate phase, the comparator output will make a HIGH-to-LOW transition as the integrator output ramp crosses zero. The transition is used to signal the processor that the conversion is complete. The internal comparator delay is 2sec, typically. Figure 5 shows the comparator output for large positive and negative signal inputs. For signal inputs at or near zero volts, however, the integrator swing is very small. If commonmode noise is present, the comparator can switch several times during the beginning of the signal-integrate period. To ensure that the polarity reading is correct, the comparator output should be read and stored at the end of the signal integrate phase. The comparator output is undefined during the AutoZero Phase and is used to time the Integrator Output Zero phase. (See Integrator Output Zero Phase of System Timing section).
1
2 3 4
SIGNAL INTEGRATE INTEGRATOR OUTPUT
REFERENCE DEINTEGRATE
SIGNAL INTEGRATE
REFERENCE DEINTEGRATE
ZERO CROSSING INTEGRATOR OUTPUT ZERO CROSSING COMPARATOR OUTPUT COMPARATOR OUTPUT
5 6
A. Positive Input Signal
B. Negative Input Signal
Figure 5. Comparator Output
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TC500 TC500A TC510 TC514
APPLICATIONS Component Value Selection
The procedure outlined below allows the user to arrive at values for the following TC5xx design variables: (1) (2) (3) (4) Integration Phase Timing Integrator Timing Components (RINT, CINT) Auto Zero and Reference Capacitors Voltage Reference
PRECISION ANALOG FRONT ENDS
Table 1. CREF and CAZ Selection Conversions Typical Value of Suggested * Per Second CREF, CAZ (F) Part Number >7 2 to 7 2 or less 0.1 0.22 0.47 WIMA MK12 .1/63/20 WIMA MK12 .22/63/20 WIMA MK12 .47/63/20
*WIMA Corp. listing on the last page of this data sheet.
Select Integration Time Integration time must be picked as a multiple of the period of the line frequency. For example, tINT times of 33msec, 66msec and 132msec maximize 60Hz line rejection. DINT and IZ Phase Timing The duration of the DINT phase is a function of the amount of voltage stored on the integrator during TINT, and the value of VREF. The DINT phase must be initiated immediately following INT and terminated when an integrator output zero-crossing is detected. In general, the maximum number of counts chosen for DINT is twice that of INT (with VREF chosen at VIN (max)/2). Calculate Integrating Resistor (RINT) The desired full-scale input voltage and amplifier output current capability determine the value of RINT. The buffer and integrator amplifiers each have a full-scale current of 20A. The value of RINT is therefore directly calculated as follows: V RINT(in M) = IN MAX 20 where: VIN MAX = Maximum input voltage (full count voltage) RINT =Integrating Resistor (in M) For loop stability, RINT should be 50k. Select Reference (CREF) and Auto Zero (CAZ) Capacitors CREF and CAZ must be low leakage capacitors (such as polypropylene). The slower the conversion rate, the larger the value CREF must be. Recommended capacitors for CREF and CAZ are shown in Table 1. Larger values for CAZ and CREF may also be used to limit roll-over errors.
Calculate Integrating Capacitor (CINT) The integrating capacitor must be selected to maximize integrator output voltage swing. The integrator output voltage swing is defined as the absolute value of VDD (or VSS) less 0.9V (i.e., VDD - 0.9V or VSS +0.9V ). Using the 20A buffer maximum output current, the value of the integrating capacitor is calculated using the following equation. (tINT) (20 x 10 -6) (VS - 0.9) where: tINT = Integration Period VS = Applied Supply Voltage CINT = (in F) = It is critical that the integrating capacitor has a very low dielectric absorption. Polypropylene capacitors are an example of one such chemistry. Polyester and Polybicarbonate capacitors may also be used in less critical applications. Table 2 summarizes recommended capacitors for CINT.
Table 2. Recommend Capacitor for CINT
Value
0.1 0.22 0.33 0.47
Suggested Part Number*
WIMA MK12 .1/63/20 WIMA MK12 .22/63/20 WIMA MK12 .33/63/20 WIMA MK12 .47/63/20
*WIMA Corp. listing on the last page of this data sheet.
Calculate VREF The reference deintegration voltage is calculated using: VREF (in Volts) = (VS - 0.9) (CINT) (RINT) 2(tINT)
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PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514
S S S
1
N
TH
INTEGRATOR OUTPUT
COMPARATOR OUTPUT COMP
INTEGRATE PHASE
DESIGN CONSIDERATIONS
Noise The threshold noise (NTH) is the algebraic sum of the integrator noise and the comparator noise. This value is typically 30V. Figure 6 shows how the value of the reference voltage can affect the final count. Such errors can be reduced by increased integration times, in the same way that 50/60Hz noise is rejected. The signal-to-noise ratio is related to the integration time (tINT) and the integration time constant (RINT) (CINT) as follows: S/N (dB) = 20 Log
30 V
2 3 4 5 6 7
NTH
NTH Normal V
REF
Low
REF
High
VREF
SLOPE (S) =
VREF N = Noise Threshold RINT CINT TH
Figure 6. Noise
ZERO CROSSING
OVERSHOOT
DEINTEGRATE PHASE INTEGRATOR ZERO PHASE
Figure 8 shows the overall timing for a typical system in which a TC5xx is interfaced to a microcontroller. The microcontroller drives the A, B inputs with I/O lines and monitors the comparator output, CMPTR, using an I/O line or dedicated timer-capture control pin. It may be necessary to monitor the state of the CMPTR output in addition to having it control a timer directly for the Reference Deintegration phase. (This is further explained below.) The timing diagram in Figure 8 is not to scale as the timing in a real system depends on many system parameters and component value selections. There are four critical timing events (as shown in Figure 8): sampling the input polarity; capturing the deintegration time; minimizing overshoot and properly executing the Integrator Output Zero phase.
Figure 7. Overshoot
Auto-Zero Phase
The length of this phase is usually set to be equal to the Input Signal Integration time. This decision is virtually arbitrary since the magnitudes of the various system errors are not known. Setting the Auto-Zero time equal to the Input Integrate time should be more than adequate to null out system errors. The system may remain in this phase indefinitely, i.e., Auto-Zero is the appropriate idle state for a TC5xx device.
Input Signal Integrate Phase
The length of this phase is constant from one conversion to the next and depends on system parameters and component value selections. The calculation of tINT is shown elsewhere in this data sheet. At some point near the end of this phase, the microcontroller should sample CMPTR to determine the input signal polarity. This value is, in effect, the Sign Bit for the overall conversion result. Optimally, CMPTR should be sampled just before this phase is terminated by changing AB from 10 to 11. The consideration here
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( 30 V 10 x
IN
-6
*
tINT (RINT) * (CINT)
)
System Timing To obtain maximum performance from the TC5xx, the overshoot at the end of the Deintegration phase must be minimized. Also, the Auto Zero phase must be terminated as soon as the comparator output returns high. (See timing diagram, Figure 8). TELCOM SEMICONDUCTOR, INC.
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PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514
is that, during the initial stage of input integration when the integrator voltage is low, the comparator may be affected by noise and its output unreliable. Once integration is well underway, the comparator will be in a defined state.
Integrator Output Zero phase
The comparator delay and the controller's response latency may result in Overshoot causing charge buildup on the integrator at the end of a conversion. This charge must be removed or performance will degrade. The Integrator Output Zero phase should be activated (AB = 00) until CMPTR goes high. It is absolutely critical that this phase be terminated immediately so that Overshoot is not allowed to occur in the opposite direction. At this point, it can be assured that the integrator is near zero. Auto Zero should be entered (AB = 01) and the TC5xx held in this state until the next cycle is begun.
Reference Deintegration
The length of this phase must be precisely measured from the transition of AB from 10 to 11 to the falling edge of CMPTR. The comparator delay contributes some error in timing this phase. The typical delay is specified to be 2sec. This should be considered in the context of the length of a single count when determining overall system performance and possible single-count errors. Additionally, Overshoot will result in charge accumulating on the integrator after its output crosses zero. This charge must be nulled during the Integrator Output Zero phase.
TIME CONVERTER STATUS
INTEGRATOR VOLTAGE
0 VINT
COMPARATOR OUTPUT
,,
AUTO -ZERO
INTEGRATE
FULL SCALE INPUT
REFERENCE DEINTEGRATE
OVERSHOOT INTEGRATOR OUTPUT ZERO
COMPARATOR DELAY
UNDEFINED
0 FOR NEGATIVE INPUT 1 FOR POSITIVE INPUT
,,
READY FOR NEXT CONVERSION (AUTO-ZERO IS IDLE STATE)
A A=0
AB INPUTS
A=1
A=1
A=0
B=1 B
B=0
B=1
B=0
CONTROLLER OPERATION
BEGIN CONVERSION WITH AUTO-ZERO PHASE
TIME INPUT INTEGRATION PHASE
CAPTURE DEINTEGRATION TIME
INTEGRATOR OUTPUT ZERO PHASE COMPLETE
SAMPLE INPUT POLARITY
TYPICALLY = tINT (POSITIVE INPUT SHOWN) NOTES The length of this phase is chosen almost arbitrarily but needs to be long enough to null out worst case errors (see text)
tINT
COMPARATOR DELAY + PROCESSOR LATENCY
MINIMIZING OVERSHOOT WILL MINIMIZE I.O.Z. TIME
Figure 8. Typical Dual Slope A/D Converter System Timing 3-30
TELCOM SEMICONDUCTOR, INC.
PRECISION ANALOG FRONT ENDS
TC500 TC500A TC510 TC514
USING THE TC510/514 Negative Supply Voltage Converter (TC510, TC514)
A capacitive charge pump is employed to invert the voltage on VDD for negative bias within the TC510/514. This voltage is also available on the V- pin to provide negative OUT bias elsewhere in the system. Two external capacitors are required to perform the conversion. Timing is generated by an internal state machine driven from an on-board oscillator. During the first phase, capacitor CF is switched across the power supply and charged to V+ . S This charge is transferred to capacitor C- OUT during the second phase. The oscillator normally runs at 100kHz to ensure minimum output ripple. This frequency can be reduced by placing a capacitor from OSC to VDD. The relationship between the capacitor value is shown in the typical characteristics curves at the end of this data sheet.
1
Design Example
Given: Required Resolution: 16 Bits (65,536 counts). Maximum VIN: 2V Power Supply Voltage: +5V 60Hz System
2 3 4 5 6 7
Step 1: Pick integration time (tINT) as a multiple of the line frequency: 1/60Hz = 16.6msec. Use 4x line frequency = 66msec Step 2: Calculate RINT RINT (in M) = VINMAX/20 = 2/20 = 100k Step 3: Calculate CINT for maximum (4V) integrator output swing: CINT (in F) = (tINT) (20 x 10 -6) / (VS - 0.9) = (.066) (20 x 10 -6) / (4.1) = .32F (use closest value: 0.33F) NOTE: TelCom recommended capacitor: WIMA p/n: MK12 .33/63/10 Step 4: Choose CREF and CAZ based on conversion rate: Conversions/sec = 1/(tAZ + tINT + 2 tINT + 2msec) = 1/(66msec + 66msec +132msec+2msec) = 3.7 conversions/sec From which CAZ = CREF = 0.22F (see Table 1) NOTE: TelCom recommended capacitor: WIMA p/n: MK12 .22/63/10 Step 5: Calculate VREF VREF (in Volts) = (VS - 0.9) (CINT) (RINT) 2(tINT) = (4.1) (0.33 x 10 -6) (105) / 2(.066) = 1.025V
Analog Input Multiplexer (TC514)
The TC514 is equipped with a four input differential analog multiplexer. Input channels are selected using select inputs (A1, A0). These are high-true control signals (i.e., channel 0 is selected when (A1, A0 = 00).
EVALUATION KIT (TC500EV)
The TC500EV consists of a pre-assembled, 4 inch by 6 inch printed circuit board that connects to the serial port of any PC or dumb terminal. Design software is also included. TC500EV helps reduce design time and optimize converter performance. Please contact your local TelCom representative for more information.
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TELCOM SEMICONDUCTOR, INC.
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PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514
1 1F CINT 0.33F CAZ 0.22F 2
VOUT CINT
-
CAP- DGND CAP + VDD
24 23 TYPICAL WAVEFORMS PIN 2 + VIN PIN 19
1F
+5V
3 4
CAZ BUF ACOM
22 21 +5V
+5V R1 10k RINT 100k
5 6
TC510
C-
+
R2 10k TC05
CREF 0.22F
REF
CMPTR
19 18
MICRO CONTROLLER
7 9 8
CREF V REF
- VREF +
PIN 2 - VIN PIN 19 INPUT+ INPUT -
A 17 B
+ VIN - VIN
R3, 10k C1 0.01F
16 15
Figure 8. TC510 Design Example (See "Design Example")
+5V 21 VDD 1
- VOUT
1F CAP CAP
+ -
24 1F 22 7 0.22F 10k 10k
+
CREF
- CREF + VREF -
6 9
10k 0.01F 8 4 3 2 16 15 5 100k 0.22F 0.33F 100k + 0.01F INPUT -
TC04
V REF
TC510
PC PRINTER PORT PORT 0378 HEX BUF 2 3 10 18 A 17 19 B CMPTR CAZ CINT V IN
- VIN +
DGND 23
ACOM
Figure 9. TC510 to IBM Compatible Printer Port 3-32
TELCOM SEMICONDUCTOR, INC.
PRECISION ANALOG FRONT ENDS
TC500 TC500A TC510 TC514
1
1 1F CINT 0.33F CAZ 0.22F +5V RINT 100k 10k 6 10k 10k TC05 C1, .01F CREF 0.22F 7 9 8
VOUT
-
CAP
-
28
2 CINT 3 4 5
DGND
27
1F
2
+ 5V
TYPICAL WAVEFORMS PIN 2
CAZ BUF ACOM
CAP + VDD A0 A1
26 25 22 19 23 22 21 18 13 INPUT 1+ INPUT 1- INPUT 2+ INPUT 2- INPUT 3+ INPUT 3- INPUT4+ INPUT4- - VIN ANALOG MUX LOGIC MICRO CONTROLLER +5V + VIN
PIN 23
C-
+
REF
CMPTR A B CH1+ CH1- CH2+ CH2- CH3+ CH3- CH4+ CH4-
CREF
+ V REF - V REF
PIN 2
3 4 5
PIN 23
TC514
17 12 16 11
15 10
Figure 10. TC514 Design Example (See "Design Example")
+5V 25 18 CH1+ VDD 1 VOUT
-
+ INPUT 1 - + INPUT 2 - + INPUT 3 - + INPUT 4 -
CAP -
28
1F 1F
13 CH1- 17 12 16 11 15 CH2+ CH2- CH3+ CH3- CH4+ VREF
+
26 CAP+ C+ C 7 0.22F 6 10k
10k
REF - REF
6
TC04
9 10k 0.01F
10 CH4- 20
TC514
- VREF
8
A0 A1 A B CMPTR 100k
ANALOG MUX CONTROL LOGIC IBM PRINTER PORT 2 PORT 0378 HEX 3 10
19 22 21 23
BUF CAZ CINT
4 3 2
0.22F
0.33F
7
ACOM
5
DGND 27
Figure 11. TC514 to IBM Compatible Printer Port
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TELCOM SEMICONDUCTOR, INC.
TC500 TC500A TC510 TC514
PRECISION ANALOG FRONT ENDS
TYPICAL PERFORMANCE CHARACTERISTICS OF INTERNAL DC-TO-DC CONVERTER
Output Voltage vs Load Current 5 4 OUTPUT VOLTAGE (V) 3 2 1 0 -1 -2 -3 -4 -5 0 10 20 30 40 50 LOAD CURRENT (mA) 60 70 80 Slope 60 TA = 25C V+ = 5V OUTPUT VOLTAGE (V) -0 TA = 25C -1 -2 -3 -4 -5 -6 -7 -8 0 2 4 6 8 10 12 14 16 18 20 OUTPUT CURRENT (mA) Output Source Resistance vs. Temperature 100 OUTPUT SOURCE RESISTANCE () 90 80 70 60 50 40 -50 V+ = 5V IOUT = 10mA Output Voltage vs. Output Current
Output Ripple vs. Load Current 200 OUTPUT RIPPLE (mV PK-PK) 175 150 125 100 75 50 25 0 0 1 2 3 4 5 6 7 8 9 10 LOAD CURRENT (mA) Oscillator Frequency vs. Capacitance 100 OSCILLATOR FREQUENCY (kHz) OSCILLATOR FREQUENCY (kHz) TA = +25C V+ = 5V 150 CAP = 10F CAP = 1F V+ = 5V, TA = 25C Osc. Freq. = 100kHz
-25
0
25
50
75
100
TEMPERATURE (C) Oscillator Frequency vs. Temperature V+ = 5V
125
10
100
75
1 1 100 OSCILLATOR CAPACITANCE (pF) 10 1000
50 -50
-25
0
25 75 50 TEMPERATURE (C)
100
125
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TELCOM SEMICONDUCTOR, INC.
PRECISION ANALOG FRONT ENDS TC500 TC500A TC510 TC514
WIMA Corporation Capacitor Representatives (Tables 1 and 2 in Applications Section)
Australia: ADILAM ELECTRONICS (PTY.) LTD. P.O. Box 664 3 Nicole Close Bayswater 3153 Tel.: 3-761-4466 Fax: 3-761-4161 Canada: R-THETA INC. 130 Matheson Blvd. East, Unit 2 Mississauga, Ont. L4Z1Y6 Tel.: 905-890-0221 Fax: 905-890-1628 Hong Kong: REALTRONICS CO. LTD. E-3, Hung-On Building 2, King's Road Tel.: 25-70-1151 Fax: 28-06-8474 India: SUSAN AGENCIES P.O. Box 2138 Srirampuram P.O. Bangalore-560 021 Tel.: 080-332-0662 Fax: 080-332-4338 Israel: M.G.R. TECHNOLOGY P.O. Box 2229 Rehavot 76121 Tel.: 972-841-1719 Fax: 972-841-4178 Japan: UNIDUX INC. 5-1-21, Kyonan-Cho Musashino-Shi Tokyo 180 Tel.: 04-2232-4111 Fax: 04-2232-0331 Malaysia: MA ELECTRONICS (M) SDN BHD 346-B Jalan Jelutong 11600 Penang Tel.: 604-281-4518 Fax: 604-281-4515 Singapore: MICROTRONICS ASSOC. (PTE.) LTD. 8, Lorong Bakar Batu 03-01, Kolam Ayer Ind. Park Singapore 1334 Tel.: 65-748-1835 Tlx: 34 929 Fax: 65-743-3065 South Africa: KOPP ELECTRONICS LIMITED P.O. Box 3853 2128 Rivonia Tel.: 011-444-2333 Fax: 011-444-1706 South Korea: YONG JUN ELECTRONIC CO. #201, Sungwook Bldg. 1460-16, Seocho-Dong Seocho-Ku Seoul, Korea Tel.: 25-231-8002 Fax: 25-231-803 Taiwan, R.O.C.: SOLOMON TECHNOLOGY CORP. 7th Floor No. 2 Lane 47, Sec. 3 Nan Kang Road Taipei Tel.: 886-2788-8989 Fax: 886-288-8275 Thailand: MICROTRONICS THAI LTD. 50/68 T.T. Court Cheng Wattana Road Amphur Pak-Kreed Nonthaburi 11120 Tel.: 66-2584-5807, Ext. 102 Fax: 66-2583-3775 USA: THE INTER-TECHNICAL GROUP, INC. WIMA DIVISION 175 Clearbrook Road P.O. Box 535 Elmsford, NY 10523-0535 Tel.: 914-347-2474 Fax: 914-347-7230 TAW ELECTRONICS, INC. 4215, W. Burbank, Blvd. Burbank, CA, 91505 Tel.: 818-846-3911 Fax: 818-846-1194
1
2 3 4 5 6 7
Venezuela: MAGNETICA, S.A. Apartado 78117 Caracas 1074 A Tel.: 58-2241-7509 Fax: 58-2241-5542
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TELCOM SEMICONDUCTOR, INC.
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